The Export Control Cascade Part 2: Building an Attack Surface

As noted in Part I of this series, the Chip Security Act (CSA)’s current path to implementation as part of the National Defense Authorization Act is inhibiting debate on this new export-control proposal designed to deal with the unintended consequences of prior measures. The lack of debate is particularly troubling because, while analysis has demonstrated the feasibility of standing up a global network to track the location of advanced semiconductors via ping-based location verification (PLV), little work exists to assess the tradeoffs associated with this solution—let alone its unintended consequences. In fact, attempting to track artificial intelligence (AI) chips via PLV could end up compromising cybersecurity.

According to an analysis by the Center for Security and Emerging Technology (CSET), the feasibility of implementing a global chip-location tracking network begins with a single system. Isolated from the host operating system, the Trusted Execution Environment (TEE) is a secure enclave that proves AI chip identity using attestation keys. TEE was designed to protect data from compromised operating systems and untrusted cloud-computing providers and to ensure that data and code are not tampered with during processing. Although it is not found on all semiconductors covered by export controls, repurposing this technology as a means of location verification could satisfy CSA requirements.

Once again, feasibility bears no guarantee as to the value of the approach, let alone its greater strategic merit. Implementing PLV through TEE modification raises real concerns about the cybersecurity posture of all computational processes using advanced semiconductors.

Creating Two Novel Attack Surfaces

Standing up a global PLV system creates two significant attack surfaces that have been glossed over in the CSA debate: the consequence of modifying the TEE to perform location attestation and the networked infrastructure of 39 to 500 landmark servers required for estimating AI chip location.

In an effort to evaluate the feasibility of modifying the TEE system to function as a chip-location tracker, CSET explores three levels in the technology stack: hardware, software, and firmware. Their analysis determined that software-based signing is the least expensive but least secure, while hardware-based signing (the most secure) cannot account for chips already in the field. CSET’s ultimate recommendation is a firmware-based approach that represents a middle ground by combining the benefits of all options; however, it appears they chose to recommend the firmware-level solution not on its merits, but because it is the least bad of the three approaches.

This analysis does not fully weigh the drawbacks of adding a communication pathway to the TEE. Adding a network path would introduce a vulnerability to the chips themselves and open up advanced computing to a host of risks that threaten data confidentiality as well as trust in the integrity of that data. This vulnerability would invalidate the purpose of the TEE altogether.

TEE is half of the equation for enabling AI chip location; the other half is the global network of landmark servers that estimate location based on ping response time. This infrastructure would present a completely new attack surface based on the CSA’s chip-location mandate. In addition to providing a networking path to every chip tracked, the infrastructure would be vulnerable to an array of uptime attacks, such as Distributed Denial of Service (DDoS) and network delay manipulation. Beyond traditional cyberattacks, countries looking to use smuggled chips could fool location estimators by simply locating the chips in areas of estimation ambiguity.

While the CSET report acknowledges the possibility of connectivity loss as a problem of ambiguity for enforcement by the Bureau of Industry and Security, it does not address what would happen if the landmark servers themselves went down instead of individual chips going offline. As targetable infrastructure with a known operator, these servers provide a central failure point compared to individual TEEs. A sustained DDoS attack could cause the entire location system to go blind, simultaneously making every tracked chip noncompliant and sowing confusion for already short-staffed enforcement agencies.

Many countries subject to export controls also control their own internal network infrastructure. With PLV estimation based on round-trip ping times, malicious actors seeking to use contraband chips could slow network traffic between the TEEs and the landmark server, making the chip appear to be in a different location altogether.

Finally, covered entities could make a geographic choice to locate chips within the area of uncertainty inherent in the PLV estimation approach. Given that the best-case accuracy of PLV estimation in CSET’s paper is a 19-mile error radius, a nation looking to leverage covered advanced AI chips could simply build data centers within this distance from nations not on the export-control list. In fact, there are already situations where PLV-based tracking would be unable to distinguish which country the chips were located in: For example, the PLV system would not be able to distinguish between chips housed at Chinese-run data centers in Johor, Malaysia, and those housed 10 miles away in Singapore.

These two attack surfaces make the PLV system overall susceptible to compromise from attackers of various sophistication. Therefore, it is important to consider the types of threat actors the system is likely to encounter when determining strategic feasibility.

What About the Threat Actor?

While added attack vectors contribute significantly to the cyber risk associated with a PLV system for global chip location, cyber risk is calculated as a product of likelihood and consequence of compromise. A threat actor could compromise the integrity of advanced computing at the hardware level via the TEE, or they could blind, spoof, or exploit the landmark servers. These consequential outcomes prove that the CSA merits further debate; however, in addition to consequence, it is important to evaluate the likelihood that an attacker could achieve these effects.

CSET’s own analysis addresses this directly, stating that “even a PLV system designed with prudent security measures could likely be subverted by a sufficiently motivated and resourced actor.” Given that we are discussing tracking measures that would monitor assets with a per-chip value of tens of thousands of dollars (and with per-rack costs over $5 million), the adversaries looking to subvert export controls are sufficiently resourced by definition. Malicious actors could certainly justify expending significant resources to compromise individual chips, which would not only render the PLV system useless, but also provide a firmware-level backdoor into TEE systems worldwide.

From a landmark server perspective, CSET acknowledges a known limitation of the PLV system: its inherent “susceptibility to spoofing by well-resourced adversaries.” Beyond sophisticated actors, uptime attacks like DDoS are among the most prevalent types of cyberattack globally and require fewer technical skills to accomplish. This means the two attack surfaces combined would accommodate the broadest range of hackers, from a hacktivist looking to shut down data centers to a unit of a nation’s armed forces. Not only could this wide range of threat actors compromise the ability to track AI chips, it would also provide a means to compromise advanced computing across the globe.

CSET’s feasibility analysis alone should raise questions regarding the strategic merit of chip tracking in general and PLV in particular. CSET admits that “any implementation of a PLV system is unlikely to withstand advanced persistent threat actors (i.e., threat actors operated by nation states or state-sponsored groups) that have the resources and expertise to identify and exploit vulnerabilities in the PLV system or to compromise the organizations that maintain the PLV system.” This sentence alone deserves particular scrutiny. The term “advanced persistent threat” was coined to describe state-sponsored hacking activities by the Chinese government. Designing a feasible system for chip-tracking in order to curb Chinese diversion efforts that is unlikely to withstand Chinese hacking attempts is an approach that is entirely devoid of strategic merit.

Conclusion

The cyber implications of mandating a PLV-based chip-tracking system via the CSA present significant unintended consequences. Even the feasibility study contributing to the tailwind pushing this bill toward passage raises a host of concerns that question the rationale of implementing any chip-tracking approach at all. These concerns demonstrate the complexity of the situation surrounding semiconductor export controls and prove that passing the CSA would suppress the level of analysis and debate needed to evaluate the bill effectively.

While introducing a worldwide cybersecurity vulnerability is risk enough, it is only one dimension of the cascade of unintended consequences that would be created by this export-control measure. The next piece in this series will examine the next escalation: what happens when policymakers find that tracking chip location has no enforcement mechanism and turn to mandating the installation of remote kill switches in advanced semiconductors.